Are 128 bits atomic accesses possible with Cortex-A35?

Hi, I am using NXP i.MX 8X (Cortex-A35, i.e. ARMv8.0-A) and I would like to know if it is possible to make atomic 128 bits read/writes between 2 cores without a retry loop (Exclusive instructions)....
Are 128 bits atomic accesses possible with Cortex-A35?

Hi, I am using NXP i.MX 8X (Cortex-A35, i.e. ARMv8.0-A) and I would like to know if it is possible to make atomic 128 bits read/writes between 2 cores without a retry loop (Exclusive instructions)....
Manipulation of 12 bit ADC data using C programming

Hi all, My current ADC configuration is such that ADLJST=0, that is ADC0H[3:0]:ADC0L[7:0]. What should I do to my code (underlined bold) below to handle both ADC0H and ADC0L ? Thank you. ...
Manipulation of 12 bit ADC data using C programming

Hi all, My current ADC configuration is such that ADLJST=0, that is ADC0H[3:0]:ADC0L[7:0]. What should I do to my code (underlined bold) below to handle both ADC0H and ADC0L ? Thank you. ...
Why do we need atomicity in ARM Architecture?

How does atomicity work with the memory accesses?