How to start Firmware separated in I-RAM and D-RAM within Cortex-M3 design kit?

Hello? I'm trying to implement the Firmware with the Cortex-M3 SoC which is separately designed I-RAM and D-RAM in Keil MDK. As you can see the above example system, AHB Interconnect have 3 slaves...
How to start Firmware separated in I-RAM and D-RAM within Cortex-M3 design kit?

Hello? I'm trying to implement the Firmware with the Cortex-M3 SoC which is separately designed I-RAM and D-RAM in Keil MDK. As you can see the above example system, AHB Interconnect have 3 slaves...
One application in separate HEX files

Hello! I have application which consist of main function and some ancillary functions with mathematics, FLASH service and SPI communications(they are in different *.c files). My task is to separate my...
One application in separate HEX files

Hello! I have application which consist of main function and some ancillary functions with mathematics, FLASH service and SPI communications(they are in different *.c files). My task is to separate my...
How and when to use separate stack pointers in a non-RTOS application?

Hi, We are developing a safety critical product based on Cortex-M4 CPU. In the Definitive Guide for ARM Cortex-M3/4 I read that it is recommended to use both (MSP and SPS) stacks even, if program does...