data & unified cache

Note: This was originally posted on 9th March 2013 at http://forums.arm.com In the A8 cache registers i see that the data cache tied to Unified cache - for enabling, cleaning etc. Any reason for this...
data & unified cache

Note: This was originally posted on 9th March 2013 at http://forums.arm.com In the A8 cache registers i see that the data cache tied to Unified cache - for enabling, cleaning etc. Any reason for this...
ARMv7-a MPU/PMSA - Unified Region (Base/Size) question

Hello, I have been reading and searching for some time and have learned a lot about the MPU on an ARMv7-a. I am attempting to use the Unified Region Base/Size registers to both limit memory access,...
ARMv7-a MPU/PMSA - Unified Region (Base/Size) question

Hello, I have been reading and searching for some time and have learned a lot about the MPU on an ARMv7-a. I am attempting to use the Unified Region Base/Size registers to both limit memory access,...
L1 data cache and unified cache disabled in AMP mode for Cortex-a7

Hello Guys, in my system ( multi core cortex- a7 ), I do not want to be in SMP mode that means it is AMP mode and i need to clear the ACTLR.SMP bit to be in AMP mode but the strange thing which i found...