• mismatch between ARMv7-M ref manual and core_cm7.h
    The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h...
  • mismatch between ARMv7-M ref manual and core_cm7.h
    The ARMv7-M reference manual notes there eight ITM trace enable registers called ITM_TER0 to ITM_TER7. However, core_cm7.h only has one ITM_TER register. Can you clarify? Is it an error in core_cm7.h...
  • ARM1136: why the mismatch between cache stalls and cache misses ??
    Something weird when I count both Instruction Cache Miss event and event 0x1 (viz. “Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an...
  • ARM1136: why the mismatch between cache stalls and cache misses ??
    Something weird when I count both Instruction Cache Miss event and event 0x1 (viz. “Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an...
  • Cycle accurate instruction set simulator for Cortex-M
    Hi, Any suggestions for a cycle accurate simulator for Cortex-M devices other than Keil. We are currently using Keil uVision and came across some issues regarding the timing of a routine and would like...