[AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?

Hello, A couple of further details on the question. Let's assume that I have a 64-bit data bus and a 32-bit address bus. A master issues a WRAP burst with AWADDR[31:0] = 32'd8 and AWSIZE[2:0]...
[AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?

Hello, A couple of further details on the question. Let's assume that I have a 64-bit data bus and a 32-bit address bus. A master issues a WRAP burst with AWADDR[31:0] = 32'd8 and AWSIZE[2:0]...
Master to Master communication in AHB

For example, I have an AHB bus with two masters: 1.ARM processor 2. Ethernet MAC , many slaves. The Ethernet MAC IP should be configured to generate the Ethernet Packets. Is there any way to use Processor...
Master to Master communication in AHB

For example, I have an AHB bus with two masters: 1.ARM processor 2. Ethernet MAC , many slaves. The Ethernet MAC IP should be configured to generate the Ethernet Packets. Is there any way to use Processor...
timer interrupt disable & enable - pending interrupts

Hi, working with a LPC1758 I´ve installed a timer. In the interrupt routine I've several values which will be updated according to the current state. Is it the right approach to disable the timer...