Why only first half of register bank is accessible in VFP's S0-31 register bank?

Hello, I am working on an ALU Supervisor with armv7-M. Everything in documentation seem to say if cp10 and cp11 are activated, s0-s31 are accessible. Everything works fine with s0-s15 Though when...
Why only half of register bank is accessible in VFP's S0-31 view of register bank?

I am optimizing a simple l2-distance calculation program target at Cortex-A7. Initially, i choose to unroll the calculation loop like below: ```c void l2_naive_f32(float *mat, uint32_t m, uint32_t n...
Why only half of register bank is accessible in VFP's S0-31 view of register bank?

I am optimizing a simple l2-distance calculation program target at Cortex-A7. Initially, i choose to unroll the calculation loop like below: ```c void l2_naive_f32(float *mat, uint32_t m, uint32_t n...
Using banked registers for FIQ

Hello According to ARM7TDMI manuals, the FIQ has banked registers R8-R12. By looking at the assembler output, I've noticed that these registers are actually not used. The compiler pushes R0-R7 to the...
Using banked registers for FIQ

Hello According to ARM7TDMI manuals, the FIQ has banked registers R8-R12. By looking at the assembler output, I've noticed that these registers are actually not used. The compiler pushes R0-R7 to the...