• Arm CPU subsystem development process
    Hi I need some help/pointers regarding Arm based CPU subsystem design. Our team works on Arm based CPU subsystem design. It includes integrating Arm CPU cores, building AXI/AHB bus interconnects,...
  • Arm CPU subsystem development process
    Hi I need some help/pointers regarding Arm based CPU subsystem design. Our team works on Arm based CPU subsystem design. It includes integrating Arm CPU cores, building AXI/AHB bus interconnects,...
  • Can we reset L2 subsystem for cortex-A57?
    My system hosts 4x clusters, each with 4x cpus A57 connected through interconnect CCN504. I have a special case in which I need to reset L2 sybsystem (L2 is 2MB in my case) from inside SPL Uboot running...
  • Can we reset L2 subsystem for cortex-A57?
    My system hosts 4x clusters, each with 4x cpus A57 connected through interconnect CCN504. I have a special case in which I need to reset L2 sybsystem (L2 is 2MB in my case) from inside SPL Uboot running...
  • Is the Corelink SSE-200 Subsystem available for Cortex M23?
    This question was raised in the ' How to implement a secure IoT system on ARMv8-M ' webinar, view all the questions in the round up blog post .