ARM Bootloader: flush D/I-cache, disable D-cache and enable I-cache

Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this: mov R0, #0 mcr P15, 0, R0, C7, C7, 0 ; flush v3/v4 caches mcr P15, 0, R0, C8...
ARM Bootloader: flush D/I-cache, disable D-cache and enable I-cache

Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this: mov R0, #0 mcr P15, 0, R0, C7, C7, 0 ; flush v3/v4 caches mcr P15, 0, R0, C8...
A8: Keeping Cache-enabled and MMU-disabled

Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...
A8: Keeping Cache-enabled and MMU-disabled

Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...
atomic - LPC313x

Hello to everyone, can anyone please advise me whether it exists a way to execute on an LPC313x more than one instruction atomically (like for instance _atomic_ for C16x)? Thanks and best regards...