Instruction cpsie i and bx LR is not atomic.

Hi All, I have a proprietary OS Implemented in our Project and its running on ARM Cortex M7. To exit ISR handler we use these 2 instructions. cpsie i bx LR The sequence of the flow is as follows...
Instruction cpsie i and bx LR is not atomic.

Hi All, I have a proprietary OS Implemented in our Project and its running on ARM Cortex M7. To exit ISR handler we use these 2 instructions. cpsie i bx LR The sequence of the flow is as follows...
Detecting a pending interrupt before cpsie i instruction

Don't know, whether the question is put right, anyway, I'm debugging an assembler program. The effect is, that as soon as I enable interrupts using the "cpsie i" instruction, an exception (code=5, buserror...
selected processor does not support `cpsid i' and `cpsie i' in arm mode.

hi everyone, i'm new with ARMprocessor and dont know too much about DS-5. just alittle bit from my Softwares >>> SoC EDS 17.1 (from Altera) - DS-5 5.28 and my OS is Windows 10. I am using DS-5 for my...
selected processor does not support `cpsid i' and `cpsie i' in arm mode.

hi everyone, i'm new with ARMprocessor and dont know too much about DS-5. just alittle bit from my Softwares >>> SoC EDS 17.1 (from Altera) - DS-5 5.28 and my OS is Windows 10. I am using DS-5 for my...