• How does cache system work when Dual-Core Lockstep mode in Cortex-A76AE is activated.
    Dear Forum, Could some one explain how the cache system works when DCLS is activated on Cortex-A76AE? As both cores serve as logically one core and provide the error check ability, all the registers...
  • Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?
    As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode. I'm curious about the handling of Interrupt Service Routine during the lock-step mode. ...
  • Is that possible for Cortex-R5's dual-core to handle interrupt during lock-step mode?
    As I know, Cortex-R5MP supports lock-step mode and every output from two cores will be compared in this mode. I'm curious about the handling of Interrupt Service Routine during the lock-step mode. ...
  • I need support to initialize GICv2 on ARM A53 Dual Core processor environment in Non Secure mode.
    Hi, I'm trying to initialize the GICv2 interrupt controller to manage interrupts coming in the systems. At the moment I'm not able to receive interrupts on the CPU. It seems to me that these interrupts...
  • ADC Counts are correct in debugging mode but not in normal mode
    I am working on ADS1241 24 bit ADC. My ADC counts are correct in debugging mode but not in normal mode with or without breakpoints.I am using Keil uvision5 and STLink Debugger.