Startup file for AT91SAM9260 -- Master Clock Register

Hi, I'm a little bit confused about the startup file for the AT91SAM9260. Under "Power Management Controller (PMC)"->"Master Clock Register (CKGR_MCKR)"->MDIV: Master Clock Division" one can select...
Startup file for AT91SAM9260 -- Master Clock Register

Hi, I'm a little bit confused about the startup file for the AT91SAM9260. Under "Power Management Controller (PMC)"->"Master Clock Register (CKGR_MCKR)"->MDIV: Master Clock Division" one can select...
Master to Master communication in AHB

For example, I have an AHB bus with two masters: 1.ARM processor 2. Ethernet MAC , many slaves. The Ethernet MAC IP should be configured to generate the Ethernet Packets. Is there any way to use Processor...
Master to Master communication in AHB

For example, I have an AHB bus with two masters: 1.ARM processor 2. Ethernet MAC , many slaves. The Ethernet MAC IP should be configured to generate the Ethernet Packets. Is there any way to use Processor...
MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave

Hi, Facing the issue: "MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave" Here is the Inputs: We are using the custom SOC, in which we are testing...