Data abort exception for unaligned access in Cortex A55

Hi, I have written a simple assembly code in Cortex A55, which executes in EL3, 64-bit execution state. In the code, the cache and MMU is disabled which means that any memory accessed will be treated...
Data abort exception for unaligned access in Cortex A55

Hi, I have written a simple assembly code in Cortex A55, which executes in EL3, 64-bit execution state. In the code, the cache and MMU is disabled which means that any memory accessed will be treated...
Cortex M4 Unaligned access with STR single word access

Hi there, I am getting a hard fault for accessing an unaligned memory address with STR single word access on a cortex M4 processor (Infineon XMC4500 F100k1024). Cortex M4 manual says that: Unaligned support...
Cortex M4 Unaligned access with STR single word access

Hi there, I am getting a hard fault for accessing an unaligned memory address with STR single word access on a cortex M4 processor (Infineon XMC4500 F100k1024). Cortex M4 manual says that: Unaligned support...
Unaligned accesses - CMSDK Example Cortex M0

The spec mentions that the M0 will generate a Hardfault when unaligned accesses are detected. I would like to find out where is this implemented in RTL and understand it a little better. Does the...