As arm cortex R4 is a dual core processor, is there a concept of booting core (primary core) and secondary core?

Cortex R4 processor architecture mentions the processor as dual core. Is there a concept of booting core(primary core) and secondary core? Please provide details on this aspect.
As arm cortex R4 is a dual core processor, is there a concept of booting core (primary core) and secondary core?

Cortex R4 processor architecture mentions the processor as dual core. Is there a concept of booting core(primary core) and secondary core? Please provide details on this aspect.
SMP ARM cores hang when using DMA and two cores enabled

Hi, I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA. I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode. SOC used is Altera Cyclone...
SMP ARM cores hang when using DMA and two cores enabled

Hi, I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA. I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode. SOC used is Altera Cyclone...
How does the ARM CA53 4 core join NEON on only 2 cores?

Our project only wants 2 cores to support NEON for cost reasons. How can I do this? 1. Can a single cluster be done? 2. Cut into 2 clusters, each with 2 cores. What is the difference between the performance...