Simulating an I2C master

I am developing an application that functions as an I2C slave. To test it, I am trying to write a debug function to simulate the I2C master. With what I have so far, I successfully start I2C communication...
Simulating an I2C master

I am developing an application that functions as an I2C slave. To test it, I am trying to write a debug function to simulate the I2C master. With what I have so far, I successfully start I2C communication...
Verilog bus functional models for AHB master simulation

I see in the documentation site that ARM offers up some bus functional models to simulate both a 32 and a 64 bit AHB bus master in Verilog RTL. Where do I find these models, and what is the cost? I am...
Verilog bus functional models for AHB master simulation

I see in the documentation site that ARM offers up some bus functional models to simulate both a 32 and a 64 bit AHB bus master in Verilog RTL. Where do I find these models, and what is the cost? I am...
Master to Master communication in AHB

For example, I have an AHB bus with two masters: 1.ARM processor 2. Ethernet MAC , many slaves. The Ethernet MAC IP should be configured to generate the Ethernet Packets. Is there any way to use Processor...