What does "low interrupt latency" means

Hi All, In R4 trm, there are some words about low interrupt latency. I have a question about it. " Low interrupt latency On receipt of an interrupt, the processor abandons any pending restartable memory...
What does "low interrupt latency" means

Hi All, In R4 trm, there are some words about low interrupt latency. I have a question about it. " Low interrupt latency On receipt of an interrupt, the processor abandons any pending restartable memory...
the means of tail-chaining of interrupts

hellow I am reading the book “Cortex -M3 Embedded Software Development” on page of 3,chapter 1.1 Nested Vectored Interrupt Controller (NVIC), i don not understand the means of tail-chaining of interrupts...
the means of tail-chaining of interrupts

hellow I am reading the book “Cortex -M3 Embedded Software Development” on page of 3,chapter 1.1 Nested Vectored Interrupt Controller (NVIC), i don not understand the means of tail-chaining of interrupts...
what does "Synchronous exception from Current EL with SP_ELx" mean?

In here : https://chromium.googlesource.com/external/github.com/ARM-software/arm-trusted-firmware/+/v0.4-rc1/docs/firmware-design.md#bl1-architectural-initialization The arm-tf B1 code sets the LED...