• Bootcode geneartion from C testcase for Cortex_R4
    Have existing setup for CortexM3 to generate bootcode from C tetscases. Able to use same setup  to generate bootcode for Cortex-M4 with minimum changes. But seeing issue while using same setup for Cortex...
  • Bootcode geneartion from C testcase for Cortex_R4
    Have existing setup for CortexM3 to generate bootcode from C tetscases. Able to use same setup  to generate bootcode for Cortex-M4 with minimum changes. But seeing issue while using same setup for Cortex...
  • Some question about Debugging Code Banking Applications with MON51?
    Some question about Debugging Code Banking Applications with MON51? I have read the "Debugging Code Banking Applications with MON51" APNT_128. My bank rom is flash chip.0x0000-0x3FFF My XRAM...
  • Some question about Debugging Code Banking Applications with MON51?
    Some question about Debugging Code Banking Applications with MON51? I have read the "Debugging Code Banking Applications with MON51" APNT_128. My bank rom is flash chip.0x0000-0x3FFF My XRAM...
  • Question about application of PendSV
    Reading jyiu book on Cortex-M4 and general information about usage of PendSV exception type. One application highlighted is of context switching in the RTOS wherein on a Systick timer interrupt, instead...