How do branch instructions influence the performance of Cortex-A77?

In "Arm Cortex-A77 Core Software Optimization Guide", it says: In my understanding, it would be very difficult to predict multiple branch instructions in a 32-Byte aligned instruction memory...
How do branch instructions influence the performance of Cortex-A77?

In "Arm Cortex-A77 Core Software Optimization Guide", it says: In my understanding, it would be very difficult to predict multiple branch instructions in a 32-Byte aligned instruction memory...
AARM and offset calculation

A simple code example: AREA SOME_DATA, DATA, READWRITE, ALIGN=2 RSEG SOME_DATA MY_DATA: FIRST_VAR EQU $ - MY_DATA DSD 1 SECOND_VAR EQU $ - MY_DATA DSD 1 AREA SOME_CODE, CODE, READONLY, ALIGN...
AARM and offset calculation

A simple code example: AREA SOME_DATA, DATA, READWRITE, ALIGN=2 RSEG SOME_DATA MY_DATA: FIRST_VAR EQU $ - MY_DATA DSD 1 SECOND_VAR EQU $ - MY_DATA DSD 1 AREA SOME_CODE, CODE, READONLY, ALIGN...
How can CLZ equivalent be achieved on Cortex-M0 where this instruction is missing?

Looking for alternates for this instruction.