what happens when same interrupt comes to much fast on IRQ pin of ARM926ej-s?

In ARM926ej-s processor architecture there are two interrupt lines IRQ, FIQ. Suppose on IRQ line,interrupt comes too fast after one interrupt is latched. So is there any queue which will store pending...
what happens when same interrupt comes to much fast on IRQ pin of ARM926ej-s?

In ARM926ej-s processor architecture there are two interrupt lines IRQ, FIQ. Suppose on IRQ line,interrupt comes too fast after one interrupt is latched. So is there any queue which will store pending...
In the A15 fast model, when an unaligned (instruction) happens, will the system timer stalls too?

I have a tight loop listed as follow. thumb-2. Using the fast model. PC=0x700abdfe DISASS="MRRC p15,#0,r0,r1,c14" PC=0x700abe02 DISASS="SUBS r0,r0,r2" PC=0x700abe04 DISASS="SBC r1,r1,r3" PC...
In the A15 fast model, when an unaligned (instruction) happens, will the system timer stalls too?

I have a tight loop listed as follow. thumb-2. Using the fast model. PC=0x700abdfe DISASS="MRRC p15,#0,r0,r1,c14" PC=0x700abe02 DISASS="SUBS r0,r0,r2" PC=0x700abe04 DISASS="SBC r1,r1,r3" PC...
Detect if Interrupt Happened

I am wondering if there is a way to detect if an interrupt occurred in section of code. I know in the M3/M4/M7 I can use the LDREX/STREX to see if an exception(interrupt) occurred, is there any other...