• Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data
    Hi there, good morning. I am using TMC as Embedded Trace Fifo and testing it for FULL condition. Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF? So...
  • Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data
    Hi there, good morning. I am using TMC as Embedded Trace Fifo and testing it for FULL condition. Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF? So...
  • UART FIFO
    Hi, i got a problem with the UARTn FIFO . Can someone explain me how i get the data from this register? The manual says that, if i enable the Rx trigger level for example level3 (8 character) the...
  • UART FIFO
    Hi, i got a problem with the UARTn FIFO . Can someone explain me how i get the data from this register? The manual says that, if i enable the Rx trigger level for example level3 (8 character) the...
  • ISR FIFO Overflow
    Hi I am using a STM32F103ZG and Keil uVision + RTX. I have a multi-threaded application using interrupts and DMA. The problem I have is an intermittent ISR FIFO overflow and, upon inspection, some...