How to understand AArch64 register 'Operation' column for 'Direct access to internal memory' in Cortex -A53?

I'm reading "ARM® Cortex®-A53 MPCore Processor Technical Reference Manual". And, in 6.7 Direct access to internal memory part (P.357), there is a problem to understand what is the meaning of AArch64...
How to understand AArch64 register 'Operation' column for 'Direct access to internal memory' in Cortex -A53?

I'm reading "ARM® Cortex®-A53 MPCore Processor Technical Reference Manual". And, in 6.7 Direct access to internal memory part (P.357), there is a problem to understand what is the meaning of AArch64...
How, in a c program, do I change the data direction in a bi-directional PIO peripheral register ?

Hi, I am working with a Terasic DE0-Nano-SoC board, and am working in DS-5 Community Edition 17.1. I have created some PIO peripheral registers in Qsys / Platform Designer, connected to some well...
How, in a c program, do I change the data direction in a bi-directional PIO peripheral register ?

Hi, I am working with a Terasic DE0-Nano-SoC board, and am working in DS-5 Community Edition 17.1. I have created some PIO peripheral registers in Qsys / Platform Designer, connected to some well...
Direct Addressing

I am using 89c51. In ASM when I use the command to access the direct address, in some cases its work perfectly but in some case its didnâ€™t work When I use this command MOV 80H, #0d ...