• Additional memory cycles during LDR with unaligned address
    When LDR makes an unaligned memory access on a Cortex-M4 (ARMv7), I would expect there to be two memory read cycles required to retrieve the data. More specifically, I would expect that to be true whether...
  • Additional memory cycles during LDR with unaligned address
    When LDR makes an unaligned memory access on a Cortex-M4 (ARMv7), I would expect there to be two memory read cycles required to retrieve the data. More specifically, I would expect that to be true whether...
  • Can I expand additional code & data memory for P89LPC932 ?
    In micro-Vision IDE attached to LPC900 Development Studio, the Device/Target menu shows the possibility of expanding off-chip code memory(EPROM) & off-chip Xdata memory(RAM). How to realize it? Does P89LPC932...
  • Can I expand additional code & data memory for P89LPC932 ?
    In micro-Vision IDE attached to LPC900 Development Studio, the Device/Target menu shows the possibility of expanding off-chip code memory(EPROM) & off-chip Xdata memory(RAM). How to realize it? Does P89LPC932...
  • Using monitor in EZ-USB FX w/o additional memory
    I have a tiny system with no external memory. What I've learned from the monitor map file (mon-int-sio0.m51) there are a couple of gaps. As I'm running out of memory with my application, how could I link...