Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

Hi Experts, I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC. While multi-core testing, I'm facing some wired problem on my world shared memory mechanism. When I run world shared memory...
Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

Hi Experts, I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC. While multi-core testing, I'm facing some wired problem on my world shared memory mechanism. When I run world shared memory...
AHB Bufferable/Non-bufferable write

Note: This was originally posted on 12th September 2008 at http://forums.arm.com Hi, Please clarify the following issue related to AHB write: If HPROT[2] = 1, AHB write is bufferable and we need to provide...
AHB Bufferable/Non-bufferable write

Note: This was originally posted on 12th September 2008 at http://forums.arm.com Hi, Please clarify the following issue related to AHB write: If HPROT[2] = 1, AHB write is bufferable and we need to provide...
Memory Corruption Issues

Hi, I am using an audio module for 3d sound effects where I will be using around 20 pair(for Left and Right Channels) of coefficient buffers of size 200. I could able to run this code on M7 and got...