Cortex-M33 - SVC call from non-secure code does not trigger non-secure SVC exception

Hello, I am trying to do a proof-of-concept running the Apache NuttX RTOS on STMicroelectronic's ST32L562E-DK board as the non-secure application with TrustedFirmware-M (ST's port of TF-M provided with...
Cortex-M33 - SVC call from non-secure code does not trigger non-secure SVC exception

Hello, I am trying to do a proof-of-concept running the Apache NuttX RTOS on STMicroelectronic's ST32L562E-DK board as the non-secure application with TrustedFirmware-M (ST's port of TF-M provided with...
How does ARM11 respond to a non-secure interrupt in secure mode?

Note: This was originally posted on 19th March 2009 at http://forums.arm.com Hi All, Assuming that ARM11 is running a secure process and receives a non-secure IRQ or FIQ, how does ARM11 respond to a non...
Does CCI-400 guarantees cache coherency between secure and non-secure worlds?

Hi Experts, I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC. While multi-core testing, I'm facing some wired problem on my world shared memory mechanism. When I run world shared memory...
How does ARM11 respond to a non-secure interrupt in secure mode?

Note: This was originally posted on 19th March 2009 at http://forums.arm.com Hi All, Assuming that ARM11 is running a secure process and receives a non-secure IRQ or FIQ, how does ARM11 respond to a non...