Enabling Software Generated Interrupts (GICv2)

Hello All, We are trying to enable/generate software generated interrupts in ZCU102. We are using following sequence to write to the GIC Registers - Read(0xF9020000) -- Reading GICC_CTLR gives the...
Interrupt signal Bypass in GICv2

Hi all, ARM® Generic Interrupt Controller - Architecture version 2.0 In GICv2 (2.3.1 Interrupt signal bypass, and GICv2 bypass disable --- Page 2-27) it is mentioned that CPU interface optionally includes...
Enabling Software Generated Interrupts (GICv2)

Hello All, We are trying to enable/generate software generated interrupts in ZCU102. We are using following sequence to write to the GIC Registers - Read(0xF9020000) -- Reading GICC_CTLR gives the...
Interrupt signal Bypass in GICv2

Hi all, ARM® Generic Interrupt Controller - Architecture version 2.0 In GICv2 (2.3.1 Interrupt signal bypass, and GICv2 bypass disable --- Page 2-27) it is mentioned that CPU interface optionally includes...
GICv2 Interrupt auto deassertion - Cortex-R5

Hi, I am using an SOC with GIC (probably v2) on Cortex-R. I have timer interrupt at IRQ#226. I have enabled it in distributor block and cpu block in Group#1. The moment I enable the interrupt it is...