mmu page table

Note: This was originally posted on 22nd April 2013 at http://forums.arm.com hi some question about MMU table. background: 1.the CPU is ARM1176JS-Z. 2. L1 cache enabled 3.i want to enable MMU in bootloader...
mmu page table

Note: This was originally posted on 22nd April 2013 at http://forums.arm.com hi some question about MMU table. background: 1.the CPU is ARM1176JS-Z. 2. L1 cache enabled 3.i want to enable MMU in bootloader...
arm MMU-500 code samples

Hello. I am looking for sample source code to understand how to program the MMU-500 SMMU. The MMU-500 Technical Reference Manual (DDI0517F) does not contain any code samples. Our processor is arm...
arm MMU-500 code samples

Hello. I am looking for sample source code to understand how to program the MMU-500 SMMU. The MMU-500 Technical Reference Manual (DDI0517F) does not contain any code samples. Our processor is arm...
Enable and disable MMU page table caching in L2

Hello, I am using a dual core Cortex A9 CPU and I want to enable MMU caching in L2. By default all the DDR memory region is set as non-cacheable. But then I want only the DDR regions allocated...