Exception Level Switch in ARMv8

HI there: i am developing on a ARMv8 a57 based CPU, i want to disable the cache mechanism. it seems i need the access the corresponding registers in EL1 or above. i wonder how could i switch the EL...
Exception Level Switch in ARMv8

HI there: i am developing on a ARMv8 a57 based CPU, i want to disable the cache mechanism. it seems i need the access the corresponding registers in EL1 or above. i wonder how could i switch the EL...
Exceptions levels in the ARMv8 architecture

Hello There are four exceptions levels in the ARMv8 architecture. EL0 EL1 EL2 EL3 Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure...
Confusion about exception level of ARMv8

Hi, I am fairly new to ARM processor and start work with cortexA57 recently. After reading the technical manual and programmer guide , I have some questions regarding the exception level of v8. 1. How...
Exceptions levels in the ARMv8 architecture

Hello There are four exceptions levels in the ARMv8 architecture. EL0 EL1 EL2 EL3 Can anyone explain more of the EL3 execption level? What does it mean by 'allows swtiching between secure and nonsecure...