Embedded Multi-core inter communication

Hi All, I have a question on how ARM cores communicate internally with other cores and peripherals through AXI, AHPB busses ? lets say one core wants to send the data to another core, how is this...
Embedded Multi-core inter communication

Hi All, I have a question on how ARM cores communicate internally with other cores and peripherals through AXI, AHPB busses ? lets say one core wants to send the data to another core, how is this...
What will happen if one core sends SGI interrupt to another core quickly and continuously？

I am doing this on GICv2 controller: send SGI interrupt from core0 to core1 quickly and continuously. It looks that some interrupts are missing in core1 It seems that ARM does not provide guidance in...
What will happen if one core sends SGI interrupt to another core quickly and continuously？

I am doing this on GICv2 controller: send SGI interrupt from core0 to core1 quickly and continuously. It looks that some interrupts are missing in core1 It seems that ARM does not provide guidance in...
GICv3 -- accessing the redistributors of other cores

In GICv2, per-core interrupts (SGIs and PPIs) are configured through banked registers in the distributor, which means that a core cannot access the configuration of the SGIs and PPIs of the other cores...