is it possible to flush/invalidate cache from user space for AARCH32

Hi, When AARCH64 works at AARCH32 mode, is it possible to flush/invalidate cache from user space? i know AARCH64 can do that, but is it capable for AARCH32? i am working on a user space driver and i need...
is it possible to flush/invalidate cache from user space for AARCH32

Hi, When AARCH64 works at AARCH32 mode, is it possible to flush/invalidate cache from user space? i know AARCH64 can do that, but is it capable for AARCH32? i am working on a user space driver and i need...
ARM Cortex A8 L2 Cache Flush Invalidate

Hi, I am working on DM37xevm platform and already invalidate the L2 cache (256KB) using the code asm volatile moveq r12, #0x1"); asm volatile ("smc #1...
ARM Cortex A8 L2 Cache Flush Invalidate

Hi, I am working on DM37xevm platform and already invalidate the L2 cache (256KB) using the code asm volatile moveq r12, #0x1"); asm volatile ("smc #1...
Flushing all L1 & L2 caches under Linux (kernel space) - optimizing dma-mapping API

Hi, In my system (CycloneV - 2 cores of Cortex-A9) I require large DMA transfers, and currently I can't connect DMA via ACP, so cache coherency becomes SW problem. I know that the proper way of doing...