• Having multiple different segments for the constants in a single module
    Hi, I have multiple arrays of function pointers (say arr1[] and arr2[]) in a module (say mod1). Some functions in arr1[] is calling a function (say func_a()), which is calling some functions...
  • Having multiple different segments for the constants in a single module
    Hi, I have multiple arrays of function pointers (say arr1[] and arr2[]) in a module (say mod1). Some functions in arr1[] is calling a function (say func_a()), which is calling some functions...
  • Decoding the DRAM addressing from AXI byte addressing on PS side of ARM Cortex A53
    Hello, I am using the ZCU102 Ultrascale+ board and have replaced the default DDR memory with 32 GB - DDR4 (row address bits: 17, dual rank, column bits: 10, Bank group: 2 bits, Bank Address: 2 bits...
  • Decoding the DRAM addressing from AXI byte addressing on PS side of ARM Cortex A53
    Hello, I am using the ZCU102 Ultrascale+ board and have replaced the default DDR memory with 32 GB - DDR4 (row address bits: 17, dual rank, column bits: 10, Bank group: 2 bits, Bank Address: 2 bits...
  • What's the single cycle Load-Use in ALU mean?(In Cortex-A7)
    What's the single cycle Load-Use in ALU mean? This is in the follow picture: