• Question about AXI Wrapping burst
    There is a statement ' For wrapping burst, the length of the burst must be 2,4,8 or 16 transfers. ' in AXI Addressing option. I cannot understand that why must be 2,4,8 or 16 transfers? Is there some...
  • Question about AXI Wrapping burst
    There is a statement ' For wrapping burst, the length of the burst must be 2,4,8 or 16 transfers. ' in AXI Addressing option. I cannot understand that why must be 2,4,8 or 16 transfers? Is there some...
  • Question about AXI Exclusive Access Process
    Let's think about the case that a master issues a exclusive write transaction to a slave. On the AXI Specifiaction document, it says that if the slave doesn't support "Exclusive Accesss", then it will...
  • Question about AXI Exclusive Access Process
    Let's think about the case that a master issues a exclusive write transaction to a slave. On the AXI Specifiaction document, it says that if the slave doesn't support "Exclusive Accesss", then it will...
  • I have a question about cache operations.
    The system has been set up to be software coherent. A single coherent domain contains two A15 cores and L2. When cores 0 and 1 are reading/writing the same cache line, what happens if core 0 does a cache...