is it possible to flush/invalidate cache from user space for AARCH32

Hi, When AARCH64 works at AARCH32 mode, is it possible to flush/invalidate cache from user space? i know AARCH64 can do that, but is it capable for AARCH32? i am working on a user space driver and i need...
is it possible to flush/invalidate cache from user space for AARCH32

Hi, When AARCH64 works at AARCH32 mode, is it possible to flush/invalidate cache from user space? i know AARCH64 can do that, but is it capable for AARCH32? i am working on a user space driver and i need...
ARM Context ID Register & Process Context Switch

Hi, all What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value of Process ID and ASID? As far as I know, it is so in Linux. Is that the same...
ARM Context ID Register & Process Context Switch

Hi, all What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value of Process ID and ASID? As far as I know, it is so in Linux. Is that the same...
ARM Bootloader: flush D/I-cache, disable D-cache and enable I-cache

Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this: mov R0, #0 mcr P15, 0, R0, C7, C7, 0 ; flush v3/v4 caches mcr P15, 0, R0, C8...