aarch64 MMU: skipping first/second level tables

Hi ! on armv7 [1] / aarch32 [2] MMU, when using Long descriptor, when the virtual space described by ttbr0 is small enough (1Gb here), the level 1 translation can be skipped, leaving only two levels...
aarch64 MMU: skipping first/second level tables

Hi ! on armv7 [1] / aarch32 [2] MMU, when using Long descriptor, when the virtual space described by ttbr0 is small enough (1Gb here), the level 1 translation can be skipped, leaving only two levels...
Dual A53 cluster, MMU configuration

Hello, we have a A53 cluster with two cores, core 0 and core 1. is there any possibility that the MMU configuration of core 1 is only done by core 0?since on core 1 a non secure application is running...
Cortex-A53 - Understanding Translation Table (Cannot enable MMU)

Hello, I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :( I created following tables: Level 1 0 0000000010006003 1 0000000010007003 2 0000000010008003...
Cortex-A53 - Understanding Translation Table (Cannot enable MMU)

Hello, I'm trying to get MMU working on Cortex-A53. But still fails since at least 3 days. :( I created following tables: Level 1 0 0000000010006003 1 0000000010007003 2 0000000010008003...