Enabling MMU crashes ARM Cortex A7

I am working on smp_prime code of ARM - A9. And a i want to use that code for cortex A7. But after making changes like setting smp bit in ACTLR, Making the memory region device and non coherent- then...
Enabling MMU crashes ARM Cortex A7

I am working on smp_prime code of ARM - A9. And a i want to use that code for cortex A7. But after making changes like setting smp bit in ACTLR, Making the memory region device and non coherent- then...
A8: Keeping Cache-enabled and MMU-disabled

Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...
Permission fault, level 2 on MMU enable

Hi ARM folks, hoping someone can show me where I'm going wrong programming the MMU. The ESR_EL1 reports that it is a Permission fault, level 2. Here's what I'm trying to accomplish: 4GiB space, 4kiB...
A8: Keeping Cache-enabled and MMU-disabled

Hi all, A Question about the A8 processor. If I enable the L1 and L2 caches, I see a performance boost even if the MMU is disabled. I was under the impression that the MMU is required to be enabled...