Virtual IRQ/FIQ exceptions with ARMv8 and no GIC

Hello All, I had a couple of clarifications w.r.t the ARMv8 docs and Virtual IRQ/FIQ exceptions in conjunction with HCR.{IMO,FMO} bits and interrupt routing. A) Does this mechanism require a GIC or can...
Virtual IRQ/FIQ exceptions with ARMv8 and no GIC

Hello All, I had a couple of clarifications w.r.t the ARMv8 docs and Virtual IRQ/FIQ exceptions in conjunction with HCR.{IMO,FMO} bits and interrupt routing. A) Does this mechanism require a GIC or can...
ARMv8-M - toolchains / virtual platforms

Hello, I would be interested to try the new features of the ARMv8-M architecture, in particular v8-M TrustZone, but I can't find necessary tools in order to do so. 1. I need a toolchain that supports...
ARMv8-M - toolchains / virtual platforms

Hello, I would be interested to try the new features of the ARMv8-M architecture, in particular v8-M TrustZone, but I can't find necessary tools in order to do so. 1. I need a toolchain that supports...
Data Cache Zero by Virtual Address (DC ZVA) instruction

HI Everyone, i have been trying to test whether or not DC ZVA instruction causes an L1 or L2 cache allocation on Cortex-A73. The ARMv8-A architecture reference manual makes no statements about whether...