How to get the pipelines stages of the thunderX2 vulcan Micro-architecture like in the classic RISC 5 stages with the corresponding stages names?

Hi all, I am working on ARM Marvell ThunderX2 vulcan micro-architecture and want to understand it pipelines stages names. As the classic RISC pipeline has 5 stages (named Fetch, Decode, Memory, Execute...
How to get the pipelines stages of the thunderX2 vulcan Micro-architecture like in the classic RISC 5 stages with the corresponding stages names?

Hi all, I am working on ARM Marvell ThunderX2 vulcan micro-architecture and want to understand it pipelines stages names. As the classic RISC pipeline has 5 stages (named Fetch, Decode, Memory, Execute...
Does the ThunderX CP processor support AArch32?

It's my understanding that AArch64 is supposed to be backward compatible with AArch32, at least that is what the documentation says. But, I found one (1) page at https://en.wikichip.org/wiki/cavium/thunderx...
Does the ThunderX CP processor support AArch32?

It's my understanding that AArch64 is supposed to be backward compatible with AArch32, at least that is what the documentation says. But, I found one (1) page at https://en.wikichip.org/wiki/cavium/thunderx...
What is latest status of the Arm GNU Toolchain support for Morello? (December 2022)

Where can the latest Arm GNU Toolchain be found and what is the latest status?