LDM/STM interruption of Cortex-M7.

Hi Cortex-M7 specialists. I would like to know the Cortex-M7 behaviors when requested interrupts. In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be...
LDM/STM interruption of Cortex-M7.

Hi Cortex-M7 specialists. I would like to know the Cortex-M7 behaviors when requested interrupts. In the Cortex-M3 case, LDM/STM and DIV will stop execution by interrupt requests (although those can be...
Problems with interrupting LDM/STM Cortex M4?

I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions. The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr} The ICI bits...
Problems with interrupting LDM/STM Cortex M4?

I am seeing stack corruption running a Cortex M4 that seems to be related to interrupting multicycle instructions. The interrupt occurs during a STMDB sp!, {r4, r5, r6, r7, r8, r9, sl, lr} The ICI bits...
ldm/stm with not aligned 4byte

Hi experts! I want to use ldr/str or ldm/stm to copy memory not aligned 4bytes. I know their input address should be aligned by 4 bytes. but is there any solution to use ldr/str or ldm/stm though src...