• Synchronisation Primitives and Exclusive Monitors
    Later versions of the ARM architecture, using the LDREX/STREX instruction family, use "Exclusive Monitors" for inter-processor synchronisation of Shared Memory. How are these Monitors ("Local" amd " Global...
  • Synchronisation Primitives and Exclusive Monitors
    Later versions of the ARM architecture, using the LDREX/STREX instruction family, use "Exclusive Monitors" for inter-processor synchronisation of Shared Memory. How are these Monitors ("Local" amd " Global...
  • Armv8-R AEM FVP exclusive monitor breaks when cache_state_modelled=0
    I'm running a simple bare-metal application on Armv8-R AEM FVP (FVP_BaseR_AEMv8R 11.20.15). For the same exact code on the model's Armv8-A counterpart (FVP_Base_RevC-2xAEMvA), I noticed that setting cache_state_modelled...
  • ARMv8: strongly ordered memory and exclusive access
    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core. While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly...
  • ARMv8: strongly ordered memory and exclusive access
    We are developing a bare metal secure OS on a NXP LS1043a board, with a Cortex A53 v8 core. While debugging some issue with DMA, I decided to switch all kernel mapping from Normal cacheable to Strongly...