Forced Hard Fault / Bus Fault debugging Cortex M4

Hi, I am working on a software development on a nRF52832 chip from Nordic, embedding a Cortex M4. I am using Keil µVision5. Amongst other things, the nRF52832 communicates via UART with a GSM chip...
Forced Hard Fault / Bus Fault debugging Cortex M4

Hi, I am working on a software development on a nRF52832 chip from Nordic, embedding a Cortex M4. I am using Keil µVision5. Amongst other things, the nRF52832 communicates via UART with a GSM chip...
Hard Faults and MemManage Faults in Cortex m3/m4

I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated....
Hard Faults and MemManage Faults in Cortex m3/m4

I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated....
hard fault with Cortex M1

Note: This was originally posted on 24th December 2008 at http://forums.arm.com Hi all, I am developing firmware on Cortex M1 on Actel fusion FPGA.I have built the design that has sram at 0x0 location...