Pipeline Stage Read and Write

Note: This was originally posted on 5th March 2011 at http://forums.arm.com I'm still trying to understand the cycle table of the cortex A8. Most of the test I've made suppose this: - source register...
Pipeline Stage Read and Write

Note: This was originally posted on 5th March 2011 at http://forums.arm.com I'm still trying to understand the cycle table of the cortex A8. Most of the test I've made suppose this: - source register...
Does CHI protocol interface use pipelines or register slice to support long distance connections ?

Hi, I assume CHI needs to either pipeline or implement something like the AXI register slice to support long distance connections. Please confirm and where can I find relevant information for this...
Does CHI protocol interface use pipelines or register slice to support long distance connections ?

Hi, I assume CHI needs to either pipeline or implement something like the AXI register slice to support long distance connections. Please confirm and where can I find relevant information for this...
Reading A/D result register and output via SBUF

Using Infineon XC866-4FR I am trying to read two A/D channel results and printing the outputs to SBUF. The results are 255 < result6 < 32607 and result7 always 0. Here is the code: #include ...