What does the assertion "AXI_ERRS_BRESP_ALL_DONE_EOS" in "AMBA 3 AXI Protocol Checker User Guide" mean?

Dear all, In "AMBA 3 AXI Protocol Checker User Guide" there is an assertion item "AXI_ERRS_BRESP_ALL_DONE_EOS". The description about it is "All write transaction addresses are matched with a corresponding...
What does the assertion "AXI_ERRS_BRESP_ALL_DONE_EOS" in "AMBA 3 AXI Protocol Checker User Guide" mean?

Dear all, In "AMBA 3 AXI Protocol Checker User Guide" there is an assertion item "AXI_ERRS_BRESP_ALL_DONE_EOS". The description about it is "All write transaction addresses are matched with a corresponding...
How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted?

Hi all, I was trying to extract this information from the AXI specification but I didn't find any clear answer. I wonder how should an AXI component behave if an input xREADY signal is never asserted...
How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted?

Hi all, I was trying to extract this information from the AXI specification but I didn't find any clear answer. I wonder how should an AXI component behave if an input xREADY signal is never asserted...
compile time assert

Does anyone know how to write a compiletime ASSERT? If the condition is true, then don't generate any code. If it is false, then does #error Assert Failed to stop compilation. Thanks, Anh ...