Atomic instruction(e.g. LDXR, STXR) can't execute by CPU Cortex-A78

Hi All, Currently, I'm working on linux kernel bootup task on "Arm-A78" CPU. Linux kernel version : linux-kernel 5.10.39. Uboot version : U-Boot 2021.10-rc2 Currently, Uboot is execute successfully...
Atomic instruction(e.g. LDXR, STXR) can't execute by CPU Cortex-A78

Hi All, Currently, I'm working on linux kernel bootup task on "Arm-A78" CPU. Linux kernel version : linux-kernel 5.10.39. Uboot version : U-Boot 2021.10-rc2 Currently, Uboot is execute successfully...
about sub instruction

Note: This was originally posted on 25th July 2012 at http://forums.arm.com I am a new guy come to arm and I come across an instruction "SUB \reg0, \reg0, \reg1, lsl #STACK_BITS_PER_CPU". In other assembly...
about sub instruction

Note: This was originally posted on 25th July 2012 at http://forums.arm.com I am a new guy come to arm and I come across an instruction "SUB \reg0, \reg0, \reg1, lsl #STACK_BITS_PER_CPU". In other assembly...
I want to implement a can2usb device,what sub usb class should i use

hid or mass storage or others. if i use hid class ,i should't to write the driver on my windows xp os or not? is there any speed limit of the hid sub class? I use a STR710 EVAL board. thanks! cgha...