making physical memory pages not cacheable (probabaly by modifying page table entry)

I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
making physical memory pages not cacheable (probabaly by modifying page table entry)

I need to make physical memory pages uncacheable, it seems that in armv7 (I am using arm cortex A9) there are some bits that determine the memory type. we have two level translations (so we have pgd and...
ARMv8-A Trap access of EL2 TTBR to EL3

Hi all, I want to trap the non-secure access of several system registers (TTBR0_EL2, VTTBR_EL2, HCR_EL2, etc.) to EL3. However, when I look up the ARMv8-A reference manual, I cannot find some useful...
ARMv8-A Trap access of EL2 TTBR to EL3

Hi all, I want to trap the non-secure access of several system registers (TTBR0_EL2, VTTBR_EL2, HCR_EL2, etc.) to EL3. However, when I look up the ARMv8-A reference manual, I cannot find some useful...
How to set dram region to cacheable?

Note: This was originally posted on 31st October 2012 at http://forums.arm.com hi, experts: I am a newcomer to ARM world. I was working x86 platform in these years. So, i have a question about how to...