Cortex M0+ what means "optionally shifted" at some instructions like EOR (register)

I have to port some assembler code of a Cortex M4 to a Cortex M0+. At the Cortex M4 this was used: EOR R3,R3,R6,LSL #16 For the M0+ the arm architetcure reference v6m in chapter A6.7.23 says for...
Cortex M0+ what means "optionally shifted" at some instructions like EOR (register)

I have to port some assembler code of a Cortex M4 to a Cortex M0+. At the Cortex M4 this was used: EOR R3,R3,R6,LSL #16 For the M0+ the arm architetcure reference v6m in chapter A6.7.23 says for...
SBUF physically two registers? and shift register

My first question is regarding SBUF register of 8051. How come it is two registers while locations is only one i.e; 99H. we call SBUF physically two registers (write only and read only two separate distinct...
SBUF physically two registers? and shift register

My first question is regarding SBUF register of 8051. How come it is two registers while locations is only one i.e; 99H. we call SBUF physically two registers (write only and read only two separate distinct...
Compute the division via shift instruction

I write the code as following to evaluate the expression n = n / 2 asrs r0, r0, #1 But, I found the GCC will translate the expression n = n / 2 into the following instruction lsrs r1, r0, #31...