• ARM Cortex A8 : Enabling D Cache aborts
    I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another...
  • ARM Cortex A8 : Enabling D Cache aborts
    I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU. I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another...
  • Memory corruption in mov R4, 0; add R1, SP, #16; STB R4,[R1,#-1]! on Cortex-A9 with cache enabled, many interrupts EMAC, Timers after hours run. Not seeing in errata. R1 is not decremented and results...
    Memory corruption in mov R4, 0; add R1, SP, #16; STB R4,[R1,#-1]! on Cortex-A9 with cache enabled, many interrupts EMAC, Timers after hours run. Not seeing in errata. R1 is not decremented and results...
  • Memory corruption in mov R4, 0; add R1, SP, #16; STB R4,[R1,#-1]! on Cortex-A9 with cache enabled, many interrupts EMAC, Timers after hours run. Not seeing in errata. R1 is not decremented and results...
    Memory corruption in mov R4, 0; add R1, SP, #16; STB R4,[R1,#-1]! on Cortex-A9 with cache enabled, many interrupts EMAC, Timers after hours run. Not seeing in errata. R1 is not decremented and results...
  • ARM Bootloader: flush D/I-cache, disable D-cache and enable I-cache
    Hello everyone, I'm analysing u-boot for s3c2440(arm920t), and at the first stage u-boot does something like this: mov R0, #0 mcr P15, 0, R0, C7, C7, 0   ; flush v3/v4 caches mcr P15, 0, R0, C8...