Is increment uint32_t atomic operation

Hi, I have CMSIS RTOS thread increment uint32_t variable. Other thread is reading uint32_t variable. Do I need to use mutex to protected these read and write. Can I use any better way...
Is increment uint32_t atomic operation

Hi, I have CMSIS RTOS thread increment uint32_t variable. Other thread is reading uint32_t variable. Do I need to use mutex to protected these read and write. Can I use any better way...
M7 atomic operation faults on non cacheable memory

I'm trying to make one region of SRAM non cacheable for DMA buffers. But what I have found is that when I do that, the first atomic operation bus faults (eg RTOS mutex). Here's an example where I made...
M7 atomic operation faults on non cacheable memory

I'm trying to make one region of SRAM non cacheable for DMA buffers. But what I have found is that when I do that, the first atomic operation bus faults (eg RTOS mutex). Here's an example where I made...
C/C++ atomic operation on ARM9 and ARM Cortex-M4

I have a question about C/C++ atomic operation on ARM9 and ARM Cortex-M4. I am using ARMCC compiler with C / C++ languages. It interests me if it is possible that an interrupt will be handled in the middle...