how to connect the ACP (accelerate coherence port) interface with my SoC system

Cortex-R5 processor has an ACP interface that consisted by ACP master interface and ACP slave interface. When there is an DMA equipment in my system, the data coherency between L1 and L2 memory system...
how to connect the ACP (accelerate coherence port) interface with my SoC system

Cortex-R5 processor has an ACP interface that consisted by ACP master interface and ACP slave interface. When there is an DMA equipment in my system, the data coherency between L1 and L2 memory system...
Cache Coherence

Hi , I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid. 1. Bring Core 1 out of reset. 2. Bring Core 2 out of reset. 3. Invalidate...
IO coherency

Hello, I would like to know what is IO Coherency in ARM Cortex R5? Thanks, Surabhi
Cache Coherence

Hi , I am working on ARM Multiprocessor. The Following is scenario for Cache coherency . Please let me know if it is valid. 1. Bring Core 1 out of reset. 2. Bring Core 2 out of reset. 3. Invalidate...