• ABP wrapper/ resizer 32-128 bit FPGA SoC
    The design is implemented on a System On Chip (SoC) The processor is Cortex-M3 32-bit which is interfaced to an FPGA fabric where a processing of some variables will take place. The variables are sent...
  • ABP wrapper/ resizer 32-128 bit FPGA SoC
    The design is implemented on a System On Chip (SoC) The processor is Cortex-M3 32-bit which is interfaced to an FPGA fabric where a processing of some variables will take place. The variables are sent...
  • Are 128 bits atomic accesses possible with Cortex-A35?
    Hi, I am using NXP i.MX 8X (Cortex-A35, i.e. ARMv8.0-A) and I would like to know if it is possible to make atomic 128 bits read/writes between 2 cores without a retry loop (Exclusive instructions)....
  • Are 128 bits atomic accesses possible with Cortex-A35?
    Hi, I am using NXP i.MX 8X (Cortex-A35, i.e. ARMv8.0-A) and I would like to know if it is possible to make atomic 128 bits read/writes between 2 cores without a retry loop (Exclusive instructions)....
  • Does Cortex-A7 have the ability to send a 128-bits exclusive transaction?
    According to related manuals, I see that Cortex-A7 is able to send 8-bits, 16-bits, 32-bits, and 64-bits exclusive access. I'm wondering that if it's able to send a 128-bits exclusive access or not.