Cortex M0+ what means "optionally shifted" at some instructions like EOR (register)

I have to port some assembler code of a Cortex M4 to a Cortex M0+. At the Cortex M4 this was used: EOR R3,R3,R6,LSL #16 For the M0+ the arm architetcure reference v6m in chapter A6.7.23 says for...
Cortex M0+ what means "optionally shifted" at some instructions like EOR (register)

I have to port some assembler code of a Cortex M4 to a Cortex M0+. At the Cortex M4 this was used: EOR R3,R3,R6,LSL #16 For the M0+ the arm architetcure reference v6m in chapter A6.7.23 says for...
ARM7TDMI: SUBS vs SUB + CMP

Note: This was originally posted on 2nd April 2009 at http://forums.arm.com Hi, I have a question regarding the SUBS instruction and how it compares to SUB and CMP (due to unexpected behavior in a C-program...
ARM7TDMI: SUBS vs SUB + CMP

Note: This was originally posted on 2nd April 2009 at http://forums.arm.com Hi, I have a question regarding the SUBS instruction and how it compares to SUB and CMP (due to unexpected behavior in a C-program...