• Hard Faults and MemManage Faults in Cortex m3/m4
    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated....
  • Hard Faults and MemManage Faults in Cortex m3/m4
    I wrote a simple program, where I am writing to an illegal memory location. Writing in an illegal Memory location generates a MemManage fault. And if MemManage is not enabled, HardFault in generated....
  • MemManage Fault
    Hello, I'm looking into a Memmanage Fault which occurs in a project developed with Keil 3.40. It happens after long time after power up. The memmanage handler is B . (a branch to itself). In...
  • MemManage Fault
    Hello, I'm looking into a Memmanage Fault which occurs in a project developed with Keil 3.40. It happens after long time after power up. The memmanage handler is B . (a branch to itself). In...
  • Cortex-R5 MPU: writing to Region Base Register randomly causes Abort Exception
    Hi all, I am using MPU of Cortex-R5, in doing so when writing to Base Register, via standard CP15 access. (MCR p15, 0, Rd, c6, c1, 0) it randomly causes Prefetch Abort Exception, i.e. sometimes it works...