PL310 cache synchronization

Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
pl310 CACHE_ID register

In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register. To translate this RTL to a revision information, it is stated that "RTL release 0x9...
PL310 cache synchronization

Hi ! I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation. - when I want to perform a synchronization, should I just wait for bit 0 (bit...
pl310 CACHE_ID register

In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register. To translate this RTL to a revision information, it is stated that "RTL release 0x9...
L2 Cache(Pl310) initialisation sequence

Hi , I would like to validate L2 cache memory using U-Boot code which running on cortex-A9 dual core. Here is my L2 Cache initialisation code , While Reading/Writing to DDR Memory location, I doesn...